Non-volatile memory structure and manufacturing method thereof

ABSTRACT

A method for manufacturing a non-volatile memory structure includes providing a substrate having a gate structure, performing a first oxidation process to form a first SiO layer at least covering a bottom corner of the conductive layer, performing a first etching process to remove the first SiO layer and a portion of the dielectric layer to form a cavity, performing a second oxidation process to form a second SiO layer covering sidewalls of the cavity and a third SiO layer covering a surface of the substrate, forming a first SiN layer filling in the cavity and covering the gate structure on the substrate, and removing a portion of the first SiN layer to form a SiN structure including a foot portion filling in the cavity and an erection portion upwardly extended from the foot portion, and the erection portion covering sidewalls of the gate structure.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a non-volatile memory structure and amanufacturing method thereof, and more particularly, to asilicon-oxide-nitride-oxide-semiconductor (hereinafter abbreviated asSONOS) non-volatile memory structure and a manufacturing method thereof.

2. Description of the Prior Art

Semiconductor memory devices are prevalently used in computer andelectronics industries as a means for retaining digital information. Atypical semiconductor memory device includes a large number of memoryelements, which is known as memory cells, for storing a single digitalbit. Typically, the semiconductor memory devices are divided intovolatile and non-volatile memory devices depending on whether the datastored in the memory devices is completely lost or not in case of powerinterruption.

In the conventional non-volatile memory technology, a SONOS memorystructure is to build a silicon nitride layer sandwiched between twosilicon oxide layers for serving as the charge trap layer while the twosilicon oxide layers respectively serve as a charge tunnel layer and acharge block layer. This oxide-nitride-oxide (ONO) multilayeredstructure is further formed between a semiconductor substrate and asilicon control gate, and thus a SONOS memory structure is constructed.Since the ONO multilayered structure plays the essential role forstoring data, it is always important to form a compact ONO structure andto improve the complicated method for manufacturing the memorystructure.

SUMMARY OF THE INVENTION

According to the claimed invention, a method for manufacturing anon-volatile memory structure is provided. The method first provides asubstrate having a gate structure formed thereon, and the gate structureincludes a conductive layer and a dielectric layer. Then, a firstoxidation process is performed to form a first silicon oxide(hereinafter abbreviated as SiO) layer at least covering a bottom cornerof the conductive layer. After the first oxidation process, a firstetching process is performed to remove the first SiO layer and a portionof the dielectric layer to form a cavity under the conductive layer.After the first etching process, a second oxidation process is performedto form a second SiO layer covering sidewalls of the cavity and a thirdSiO layer covering a surface of the substrate. After the secondoxidation process, a first silicon nitride (hereinafter abbreviated asSiN) layer is formed on the substrate, and the first SiN layer fills inthe cavity and covering the gate structure. Subsequently, a portion ofthe first SiN layer is removed to form a SiN structure. The SiNstructure includes a foot portion filling in the cavity and an erectionportion upwardly extended from the foot portion. Furthermore, theerection portion covers sidewalls of the gate structure.

According to the claimed invention, a non-volatile memory structure isprovided. The non-volatile memory structure includes a substrate, a gatestructure formed on the substrate, and a SiN structure formed onsidewalls of the gate structure. The gate structure includes aconductive layer and a dielectric layer. The SiN structure includes afoot portion formed in between the gate structure and the substrate, thefoot portion inwardly extended into the gate structure and an erectionportion upwardly extended from the foot portion, the erection portioncovering the sidewalls of the gate structure.

According to the non-volatile memory structure and the manufacturingmethod thereof provided by the present invention, the foot portion ofthe SiN structure, which serves as the charge trap layer, is formed tofill up the cavity and sandwiched between two SiO layers. Thus, acompact ONO structure is easily obtained according to the presentinvention and a performance of the non-volatile memory structure istherefore always ensured.

These and other objectives of the present invention will no doubt becomeobvious to those of ordinary skill in the art after reading thefollowing detailed description of the preferred embodiment that isillustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1-7 are drawings illustrating a method for manufacturing anon-volatile memory structure provided by a first preferred embodimentof the present invention, wherein

FIG. 2 is a schematic drawing in a step subsequent to FIG. 1,

FIG. 3 is a schematic drawing in a step subsequent to FIG. 2,

FIG. 4 is a schematic drawing in a step subsequent to FIG. 3,

FIG. 5 is a schematic drawing in a step subsequent to FIG. 4,

FIG. 6 is a schematic drawing in a step subsequent to FIG. 5, and

FIG. 7 is a schematic drawing in a step subsequent to FIG. 6.

FIGS. 8-14 are drawings illustrating a method for manufacturing anon-volatile memory structure provided by a second preferred embodimentof the present invention, wherein

FIG. 9 is a schematic drawing in a step subsequent to FIG. 8,

FIG. 10 is a schematic drawing in a step subsequent to FIG. 9,

FIG. 11 is a schematic drawing in a step subsequent to FIG. 10,

FIG. 12 is a schematic drawing in a step subsequent to FIG. 11,

FIG. 13 is a schematic drawing in a step subsequent to FIG. 12, and

FIG. 14 is a schematic drawing in a step subsequent to FIG. 13.

DETAILED DESCRIPTION

FIGS. 1-7 are drawings illustrating a method for manufacturing anon-volatile memory structure provided by a first preferred embodimentof the present invention. As shown in FIG. 1, a substrate 100 isprovided. The substrate 100 includes, for example but not limited to,silicon substrate, gallium arsenide (GaAs) substrate, silicon oninsulator layer (SOI) substrate, epitaxial substrate, silicon germaniumsubstrate, or any other common semiconductor material substrate.Subsequently, a dielectric layer 102 and a conductive layer 104 aresequentially formed on the substrate 100 and followed by performing apatterning step to form a gate structure 110 on the substrate 100. Thedielectric layer 102 includes SiO and the conductive layer 104 includespolysilicon in accordance with the preferred embodiment.

Please refer to FIG. 2. Next, a first oxidation process is performed.The first oxidation process can be a rapid thermal oxidation (RTO) or beperformed in a furnace, but not limited to this. Because the conductivelayer 104 includes polysilicon material, it is oxidized during the firstoxidation process and thus a first SiO layer 120 is grown from a surfaceof the conductive layer 104 and the substrate 100. Because undercut mayoccur during etching the conductive layer 104, it is observed that thefirst SiO layer 120 is formed not only covering the surface of theconductive layer 104 but also formed at a bottom corner of theconductive layer 104 and further inwardly extending into the bottom ofthe conductive layer 104 as shown in FIG. 2.

Please refer to FIG. 3. After forming the first SiO layer 120 by thefirst oxidation process, a first etching process is performed. It isnoteworthy that an etchant used in the first etching process includesetching rates substantially different between polysilicon and SiO.Therefore, the first SiO layer 120 and a portion of the dielectric layer102 are removed and a cavity 122 is consequently formed under theconductive layer 104. As shown in FIG. 3, a portion of the bottom cornerof the conductive layer 104 is exposed in each cavity 122. It should benoted that after the first etching process, a width W₁ of the dielectriclayer 102 is smaller than a width W₂ of the conductive layer 104.

Please refer to FIG. 4. After forming the cavity 122 by the firstetching process, a second oxidation process is performed. The secondoxidation process can include RTO or be performed in a furnace, but notlimited to this. As mentioned above, since the silicon material isoxidized during the second oxidation process, a second SiO layer 130covering surface of the conductive layer 104 and sidewalls of the cavity122, and a third SiO layer 132 covering a surface of the substrate 100are formed. As shown in FIG. 4, the second SiO layer 130 covering thesidewalls of the cavity 122 is also taken as covering the bottom of theconductive layer 104 exposed in the cavity 122.

Please refer to FIG. 5. After forming the second SiO layer 130 and thethird SiO layer 132 by the second oxidation process, a first SiN layer140 is formed on the substrate 100 and the gate structure 110. It isnoteworthy that by forming the first SiN layer 140, the cavity 122 isfilled up with the SiN material as shown in FIG. 5.

Please refer to FIG. 6. Subsequently, a portion of the first SiN layer140, a portion of the second SiO layer 130 and a portion of the thirdSiO layer 132 are removed from the top surface of the gate structure 110and the surface of the substrate 100. Accordingly, a SiN structure 150is formed on the sidewalls of the gate structure 110. It is noteworthythat the SiN structure 150 includes a foot portion 152 filling in thecavity 122 and an erection portion 154 extended from the foot portion152. It is also noteworthy that foot portion 152 is formed between thegate structure 110 and the substrate 100 and the erection portion 154 isformed to cover sidewalls of the gate structure 110 as shown in FIG. 6.Additionally, because of the specific profile of the cavity 122, thefoot portion 152 of the SiN structure 150 obtains a rough triangularshape. More important, the second SiO layer 130 covering the bottom ofthe conductive layer 104, the foot portion 152 of the SiN structure 150,and the third SiO layer 132 covering the substrate 100 under the gatestructure 110 construct a spacer-type oxide-nitride-oxide (ONO)structure 160. In detail, the third SiO layer 132 serves as the chargechannel layer, the foot portion 152 of the SiN structure 150 serves asthe charge trap layer, and the second SiO layer 130 serves as the chargeblock layer. Since the ONO structure 160 is sandwiched between thesemiconductor substrate 100 and the conductive layer 104, a SONOSnon-volatile memory device 180 is obtained.

Please refer to FIG. 7. After forming the ONO structure 160, a first ionimplantation is performed to form lightly-doped drains (LDDs) 170 in thesubstrate 100 at two respective sides of the gate structure 110. Then afourth SiO layer 172 and a second SiN layer 174 are sequentially formedon the substrate 100 and followed by performing another etching process.Consequently, a spacer 176 including the fourth SiO layer 172 and thesecond SiN layer 174 is obtained on the sidewalls of the gate structure110. The spacer 176 is in contact with the SiN structure 160 and coversthe erection portion 154 of the SiN structure 150. Therefore, the fourthSiO layer 172 is sandwiched between the erection portion 154 of the SiNstructure 160 and the second SiN layer 174. After forming the spacer176, a second ion implantation is performed to form a source/drain 178in the substrate 100 at two respective sides of the gate structure 110as shown in FIG. 7.

According to the non-volatile memory structure 180 and the manufacturingmethod thereof provided by the first preferred embodiment of the presentinvention, the cavity 122 is created for accommodating the first SiNlayer 140. Therefore the ONO structure 160 formed thereafter is ensuredto have sufficient SiN material for trapping charge during programming.It is also noteworthy that by creating the cavity 122, the bottom edgeof the conductive layer 104 is rounded and thus a smooth profile isobtained for further improving electrical performance of the SONOSnon-volatile memory structure 180.

Please refer to FIGS. 8-14, which are drawings illustrating a method formanufacturing non-volatile memory structure provided by a secondpreferred embodiment of the present invention. It should be noted thatelements the same in the first and second preferred embodiments caninclude the same material choice, therefore those details are omitted inthe interest of brevity. As shown in FIG. 8, a substrate 200 isprovided. Subsequently, a dielectric layer 202 and a conductive layer204 are sequentially formed on the substrate 200 and followed byperforming a patterning step to form a gate structure 210 on thesubstrate 200. After forming the gate structure 210, an etching processis performed to remove a portion of the dielectric layer 202 to form arecess 206 in the dielectric layer 202 as shown in FIG. 8.

Please refer to FIG. 9. Next, a first oxidation process is performed toform a first SiO layer 220 on a surface of the conductive layer 204 andthe substrate 200. It is observed that the first SiO layer 220 not onlycovers the surface of the conductive layer 204 but also covers a bottomcorner of the conductive layer 204 and inwardly extends into the bottomof the conductive layer 204 as shown in FIG. 9.

Please refer to FIG. 10. After forming the first SiO layer 220 by thefirst oxidation process, a first etching process is performed. It isnoteworthy that an etchant used in the first etching process includesetching rates substantially different between polysilicon and SiO.Therefore, the first etching process is performed to remove the firstSiO layer 220 and a portion of the dielectric layer 202. Consequently,the recess 206 is deepened and a cavity 222 is formed under theconductive layer 204. It is easily conceivable that the cavity 222 shownin FIG. 10 is larger than the recess 206 shown in FIGS. 8-9. As shown inFIG. 10, a portion of the bottom corner of the conductive layer 204 isexposed in each cavity 222. It should be noted that after the firstetching process, a width W₁ of the dielectric layer 202 is smaller thana width W₂ of the conductive layer 204.

Please refer to FIG. 11. After forming the cavity 222 by the firstetching process, a second oxidation process is performed. The secondoxidation process can include RTO or be performed in a furnace, but notlimited to this. As mentioned above, since the silicon material isoxidized during the second oxidation process, a second SiO layer 230covering surface of the conductive layer 204 and sidewalls of the cavity222, and a third SiO layer 232 covering a surface of the substrate 202are formed. As shown in FIG. 11, the second SiO layer 230 covering thesidewalls of the cavity 222 is also taken as covering the bottom of theconductive layer 204 exposed in the cavity 222.

Please refer to FIG. 12. After forming the second SiO layer 230 and thethird SiO layer 232 by the second oxidation process, a first SiN layer240 is formed on the substrate 200 and the gate structure 210. It isnoteworthy that by forming the first SiN layer 240, the cavity 222 isfilled up with the SiN material as shown in FIG. 12.

Please refer to FIG. 13. Subsequently, a portion of the first SiN layer240, a portion of the second SiO layer 230, and a portion of the thirdSiO layer 232 are removed from the top surface of the gate structure 210and the surface of the substrate 200. Accordingly, a SiN structure 250is formed on the sidewalls of the gate structure 210. It is noteworthythat the SiN structure 250 includes a foot portion 252 filling in thecavity 222 and an erection portion 254 extended from the foot portion252. It is also noteworthy that foot portion 252 is formed between thegate structure 210 and the substrate 200 and the erection portion 254 isformed to cover the sidewalls of the gate structure 210 as shown in FIG.13. More important, the second SiO layer 230 covering the bottom of theconductive layer 204, the foot portion 252 of the SiN structure 250, andthe third SiO layer 232 covering the substrate 200 under the gatestructure 210 construct a spacer-type ONO structure 260. In detail, thethird SiO layer 232 serves as the charge channel layer, the foot portion252 of the SiN structure 250 serves as the charge trap layer, and thesecond SiO layer 230 serves as the charge block layer. Since the ONOstructure 260 is sandwiched between the semiconductor substrate 200 andthe conductive layer 204, a SONOS non-volatile memory device 280 isobtained.

Please refer to FIG. 14. After forming the ONO structure 260, a firstion implantation is performed to form LDDs 270 in the substrate 200 attwo respective sides of the gate structure 210. Then a spacer 276including a fourth SiO layer 272 and a second SiN layer 274 is formed onthe sidewalls of the gate structure 210. Since the steps for formingspacer 276 are the same with the first preferred embodiment, thosedetails are omitted herein for simplicity. The spacer 276 is in contactwith the SiN structure 260 and covers the erection portion 254 of theSiN structure 250. Therefore, the fourth SiO layer 272 is sandwichedbetween the erection portion 254 of the SiN structure 260 and the secondSiN layer 274. After forming the spacer 276, a second ion implantationis performed to a source/drain 278 in the substrate 200 at tworespective sides of the gate structure 210 as shown in FIG. 14.

According to the non-volatile memory structure 280 and the manufacturingmethod thereof provided by the second preferred embodiment of thepresent invention, the cavity 222 is created for accommodating the SiNmaterial. Furthermore, by forming the recess 206 before the firstoxidation process, the final cavity 222 is formed even larger and thusmore SiN material will be encompassed. Therefore the ONO structure 260formed thereafter is ensured to have sufficient SiN material fortrapping charge during programming. It is also noteworthy that bycreating the cavity 222 the bottom edge of the conductive layer 204 isrounded and thus a smooth profile is obtained for further improvingelectrical performance of the SONOS non-volatile memory structure 280.

Accordingly, the method for manufacturing the spacer type SONOSnon-volatile memory device provide by the present invention, is to formthe cavity for accommodating the SiN material and to fill up the cavitywith the foot portion of the SiN structure. As mentioned above, the footportion serving as the charge trap layer is sandwiched between two SiOlayers and thus a compact ONO structure is easily obtained according tothe present invention and a performance of the non-volatile memorystructure is therefore always ensured. Additionally, the method formanufacturing the non-volatile memory structure provided by the presentinvention has advantages of being easily integrated into thestate-of-the-art fabrication process and superior process control.

Those skilled in the art will readily observe that numerousmodifications and alterations of the device and method may be made whileretaining the teachings of the invention. Accordingly, the abovedisclosure should be construed as limited only by the metes and boundsof the appended claims.

1. A method for manufacturing a non-volatile memory structure,comprising: providing a substrate having a gate structure formedthereon, the gate structure comprising a conductive layer and adielectric layer; performing a first oxidation process to form a firstsilicon oxide (SiO) layer at least covering a bottom corner of theconductive layer; performing a first etching process to remove the firstSiO layer and a portion of the dielectric layer to form a cavity underthe conductive layer; performing a second oxidation process to form asecond SiO layer covering sidewalls of the cavity and a third SiO layercovering a surface of the substrate; forming a first silicon nitride(SiN) layer on the substrate, the first SiN layer filling in the cavityand covering the gate structure; and removing a portion of the first SiNlayer to form a SiN structure comprising a foot portion filling in thecavity and an erection portion upwardly extended from the foot portion,and the erection portion covering sidewalls of the gate structure. 2.The method for manufacturing the non-volatile memory structure accordingto claim 1, further comprising performing a second etching process toremove a portion of the dielectric layer to form a recess in thedielectric layer before the first oxidation process.
 3. The method formanufacturing the non-volatile memory structure according to claim 2,wherein the cavity is larger than the recess.
 4. The method formanufacturing the non-volatile memory structure according to claim 1,further comprising forming lightly-doped drains (LDDs) in the substrateafter forming the SiN structure.
 5. The method for manufacturing thenon-volatile memory structure according to claim 1, further comprisingforming a spacer on the sidewalls of the gate structure, and the spaceris in contact with the SiN structure.
 6. The method for manufacturingthe non-volatile memory structure according to claim 5, wherein thespacer further comprises a fourth SiO layer and a second SiN layer, andthe fourth SiO layer is sandwiched between the SiN structure and thesecond SiN layer.
 7. The method for manufacturing the non-volatilememory structure according to claim 1, further comprising forming asource/drain in the substrate at two sides of the gate structure.
 8. Themethod for manufacturing the non-volatile memory structure according toclaim 1, wherein the second SiO layer, the foot portion of the SiNstructure, and the third SiO layer construct an oxide-nitride-oxide(ONO) structure.
 9. A non-volatile memory structure comprising: asubstrate; a gate structure formed on the substrate, the gate structurecomprising a conductive layer and a dielectric layer; a cavity formed ina portion of the dielectric layer of the gate structure and a portion ofa bottom of the conductive layer of the gate structure; a SiN structureformed on sidewalls of the gate structure, the SiN structure comprising:a foot portion formed in between the gate structure and the substrate,the foot portion inwardly extended into the gate structure, and thecavity being filled with the foot portion; and an erection portionupwardly extended from the foot portion, the erection portion coveringthe sidewalls of the gate structure; and lightly doped drains (LDDs)formed in the substrate, the LDDs being not overlapped with the SiNstructure.
 10. The non-volatile memory structure according to claim 9,wherein a width of the dielectric layer is smaller than a width of theconductive layer.
 11. The non-volatile memory structure according toclaim 9, further comprising a first SiO layer covering a bottom of theconductive layer and a second SiO layer covering a surface of thesubstrate under the gate structure.
 12. The non-volatile memorystructure according to claim 11, wherein the first SiO layer, the footportion of the SiN structure, and the second SiO layer construct an ONOstructure.
 13. The non-volatile memory structure according to claim 9,further comprising a spacer covering the erection portion of the SiNstructure.
 14. The non-volatile memory structure according to claim 13,wherein the spacer further comprises a third SiO layer and a SiN layer,and the third SiO layer is sandwiched between the SiN layer and theerection portion of the SiN structure.
 15. The non-volatile memorystructure according to claim 9, further comprising a source/drain formedin the substrate.